As the performance of integrated circuits (ICs) increases, so does the amount of data transferred between ICs. The industry trend has been to transfer the data serially at very high speeds, e.g., transfer rates in excess of 1 Gigabit/second. Generally, when transferring data serially at these high speeds from a first IC to a second IC, the clock data needed to reclock the serial bit stream at the second IC is not included with the data being transferred. One approach to recover the data from the serial bit stream is to include circuitry on the second IC to regenerate the clock and recover the data. This circuitry is often referred to as a “clock recovery circuit.” Turning to FIG. 1, the serial bit stream of data, i.e., 1's and 0's, is generally comprised of a sinusoidal type signal 3. If the signal 3 is overlapped onto itself, an “eye” shape 7 is formed. Generally, the optimum point within the signal 3 to determine whether the data is a 1 or a 0 with the least amount of error is at the center 5 of the eye 7. The clock recovery circuit recovers the data by reclocking the signal 3 at as close to the center 5 of the eye 7 as possible.
One approach to performing the clock recovery is to use an analog voltage controlled oscillator (VCO) in a phase locked loop (PLL) to generate the recovered clock. In the case of multiple data streams, a disadvantage of this approach is that a VCO and a PLL is required for each input, which may consume a significant amount of area on a circuit board. Further, multiple VCOs on an IC may also increase the probability of injection locking where the VCOs will lock together.
The present invention provides a method and mechanism for regenerating the clock signal and recovering the data of a serial bit data stream. According to an embodiment, a circuit for recovering data from a serial bit stream may include a de-serializer configured for reclocking the serial bit stream using at least one reclocking signal, having a frequency with a phase, and de-serializing the serial bit stream into at least two bit streams.
The circuit, according to an embodiment, further includes a clock recovery loop filter having a second order filter coupled with the deserializer. The clock recovery loop filter may be configured for determining whether the de-serializer is reclocking the serial bit data stream at an optimum location and for generating at least one control signal to adjust the phase and frequency of at least one reclocking signal if the de-serializer is not reclocking the serial bit data stream at the optimum location. The circuit may also include a phase interpolator coupled with the clock recovery loop filter and the de-serializer, configured for generating the at least one reclocking signal in accordance with the at least one control signal.
According to another embodiment, a method for recovering data from a serial bit data stream may include regenerating at least one reclocking signal, having a frequency with a phase, to reclock the serial bit data stream; determining whether the at least one reclocking signal is reclocking the serial bit data stream at an optimum point within the serial bit data stream; if there is a frequency offset between the at least one reclocking signal and the serial bit data stream and if the serial bit data stream locks onto one value, then storing the frequency offset; and generating at least one control signal to adjust the phase of the frequency of the at least one reclocking signal to reclock at substantially near the optimum point.
Further aspects, objects, and advantages of the invention are described below in the detailed description, drawings, and claims.